TTTech Computertechnik AG is a technology leader in safety control platforms and real-time networks for Industrial IoT and aerospace applications. As part of our team your mission is to ensure safety and electronic robustness for a more connected and automated world.
 
TTTech operates under the umbrella of TTTech Group, a globally oriented group of high-tech companies. Together with their first employees, our founders started the company as spin-off of the Vienna University of Technology (TU Wien) in 1998. Today, the TTTech Group has offices in twelve different countries with more than 1,400 employees worldwide. Join our growing international team and contribute to tomorrow’s technologies today. Our Team in Brno is currently seeking for the best candidates and offer you opportunity for

Bachelor or Master Thesis (m/f)

Your Tasks/possible Topics

Topic A
Evaluation of Chisel language for use in TTTech Development Cycle. Focus on networking/TSN problems
  • https://chisel.eecs.berkeley.edu/
  • Detailed description of thesis goals could be customized based on your preferences

Topic B
Evaluation of SpinalHDL language for use in TTTech Development Cycle. Focus on networking/TSN problems

Topic C
Develop GUI application for register and memory models specification for digital design IPs
  • Generation of System Verilog UVM Register Models, C/C++/Python Header Files for SW, Datasheet generation
  • Possibility to develop as Open Source project (possible impact to whole industry)
  • TTTech provides initial requirements, examples, know-how, test cases, ...
  • Detailed description of thesis goals could be customized based on your preferences.

Topic D
Develop GUI application for VHDL/SystemVerilog IP/components interface specification
  • Generation of System Verilog/VHDL entities, structural architecture of IP, HTML documentation, IP-XACT
  • Possibility to develop as Open Source project (possible impact to whole industry)
  • TTTech provides initial requirements, examples, know-how, test cases, ...
  • Detailed description of thesis goals could be customized based on your preferences

Topic E
High level modeling of network devices

Your Profile

If you have chosen topic A & B, are you:
  • interested in digital design?
  • able to explore and learn new approaches related to digital development?
  • fan of VHDL or Verilog/SystemVerilog for Design Knowledge?
  • passionate about Ethernet, FPGAs?
 
If you have chosen topic C & D, are you:
  • interested in developing GUI applications (Qt, Java)?
  • willing to learn Java or Python/QT or C++/Qt for GUI development?
  • familiar with HTML, XML, XSLT, XSD technologies?
  • able to actively collect customer requirements and independently develop solution for it?

Our Offer

  • Exciting work environment – share our passion for high-tech innovation and cutting-edge technologies
  • Unique team spirit – join our dedicated team of international experts
  • Individual development opportunities – choose from our broad training offers and career opportunities
  • Flexible working arrangements – tailor your work according to your personal needs

We cooperate with companies such as NASA, Airbus, Boeing, Cisco, Samsung, Intel and others. In Brno we are a small team of developers based near to VUT and we are excited to give you professional guidance and help you with thesis. There is also a financial reward for good results and possibility of continuous cooperation. You are invited to come to our office and have a look what great things we do and become a part of it. Just apply now!
 
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