TTTech is a global leader in the field of robust networking and safety controls. TTTech solutions improve the safety and reliability of electronic systems in the industrial and transportation sectors, with a portfolio of products that are helping to make the Industrial Internet of Things and autonomous driving a reality.

TTTech was established in 1998 as a spin-off of the Vienna University of Technology (TU Wien). Today our company has offices in nine different countries with more than 500 employees worldwide. Our Team in Brno is currently seeking for the best candidates and offer you opportunity for

Bachelor or Master Thesis (m/f)

Your Tasks/possible Topics

Topic A
Evaluation of Chisel language for use in TTTech Development Cycle. Focus on networking/TSN problems
Topic B
Evaluation of SpinalHDL language for use in TTTech Development Cycle. Focus on networking/TSN problems

Topic C
Develop GUI application for register and memory models specification for digital design IPs
  • Generation of System Verilog UVM Register Models, C/C++/Python Header Files for SW, Datasheet generation
  • Possibility to develop as Open Source project (possible impact to whole industry)
  • TTTech provides initial requirements, examples, know-how, test cases, ...
  • Detailed description of thesis goals could be customized based on your preferences.

Topic D
Develop GUI application for VHDL/SystemVerilog IP/components interface specification
  • Generation of System Verilog/VHDL entities, structural architecture of IP, HTML documentation, IP-XACT
  • Possibility to develop as Open Source project (possible impact to whole industry)
  • TTTech provides initial requirements, examples, know-how, test cases, ...
  • Detailed description of thesis goals could be customized based on your preferences

Topic E
High level modeling of network devices

Your Profile

If you have chosen topic A, B & E, are you:
  • interested in digital design?
  • able to explore and learn new approaches related to digital development?
  • fan of VHDL or Verilog/SystemVerilog for Design Knowledge?
  • passionate about Ethernet, FPGAs?
 
If you have chosen topic C & D, are you:
  • interested in developing GUI applications (Qt, Java)?
  • willing to learn Java or Python/QT or C++/Qt for GUI development?
  • familiar with HTML, XML, XSLT, XSD technologies?
  • able to actively collect customer requirements and independently develop solution for it?

Our Offer

  • Exciting work environment – share our passion for high-tech innovation and cutting-edge technologies
  • Unique team spirit – join our dedicated team of international experts
  • Individual development opportunities – choose from our broad training offers and career opportunities
  • Flexible working arrangements – tailor your work according to your personal needs

We cooperate with companies such as NASA, Airbus, Boeing, Cisco, Samsung, Intel and others. In Brno we are a small team of developers based near to VUT and we are excited to give you professional guidance and help you with thesis. There is also a financial reward for good results and possibility of continuous cooperation. You are invited to come to our office and have a look what great things we do and become a part of it. Just apply now!
 
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